The present invention relates to analog storage arrays, and more particularly to a two-dimensional analog storage array having reduced input capacitance by disconnecting parasitic capacitances of the analog storage array from an analog signal line to provide greater speed of access.
An analog storage array is an array of switches, typically field effect transistors (FETs), and capacitors arranged so that each capacitor in turn may be connected through one or more of the switches to an analog signal line, and then disconnected to store the signal value at the time of disconnection on the selected capacitor. This type of analog storage array allows for fast and economical sampling and storing of an analog input signal for subsequent readout at a slower rate into an analog to digital converter (ADC) for digital storage. With current manufacturing technology an array of any practical size is laid out in a two-dimensional fashion. The analog signal line then becomes a multiple of "column" lines, one for each column of capacitors in the array, connected together at one end of the columns to the analog signal line to provide the same analog input signal to all capacitors. Only the particular capacitor selected by column and row stores the value of the analog input signal at that time. Such an array is disclosed in U.S. Pat. No. 4,922,452 issued May 1, 1990 to Raymond S. Larsen et al entitled " 10 Gigasample/Sec Two-Stage Analog Storage Integrated Circuit for Transient Digitizing and Imaging Oscillography hereby incorported by reference."
As shown in U.S. Pat. No. 4,922,452 each capacitor is coupled to the analog signal line by a pair of switches connected in series. The first switch in the series is a row switch, in that it turns on when that row including that cell is accessed, i.e., it turns on and off rapidly. The second switch in the series is a column switch that turns on when that column accessed, i.e., the column switch for all of the capacitors in the column are turned on and off simultaneously before and after, respectively, all of the rows have been accessed. A significant problem with analog storage arrays is the relatively large input signal capacitance which limits the speed at which the capacitors may be accessed since the capacitance has to be charged for each value stored in the array. This input capacitance has two terms: the capacitance of the capacitor(s) connected to the analog signal line at any given time, and the parasitic capacitances of the metal lines and switches. The parasitic capacitances are dominant, as only one or a few capacitors are switched to the analog signal line at a time, while all of the parasitic capacitances for the entire array of capacitors are continuously connected to the analog signal line.
What is desired is a reduced input capacitance analog storage array that minimizes the parasitic capacitances to provide higher speed sampling capabilities.